Active-HDL is a completely integrated FPGA design and verification solution, providing ease-of-use, advanced verification and debugging capabilities for today’s most complex FPGA designs. A multi-vendor flow manager controls simulation, synthesis and implementation for all devices from Actel®, Altera®. Lattice®, Quicklogic®, Xilinx® and other FPGA vendors.
Top Features:
* Graphical design entry including FPGA vendor primitives
* Mixed language HDL simulation
* Pre-compiled FPGA vendor libraries
* Automatic Testbench generation
* Import legacy designs
* Code2Graphics and Graphics2Code
* DSP design and co-simulation with MATLAB®/Simulink®
* HTML and PDF design documentation
* Code coverage analysis and Linting
* Open IP Encryption
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